Recently, demands of downsizing of electronic equipment have increased. Electronic components mounted on the electronic equipment are downsized and disposed in more proximity to each other.
When the electronic components are disposed in proximity to each other, the noise produced in the electronic component is transmitted to another electronic component directly, or via a mounting substrate or a wiring, and the normal operation of the other electronic component may be obstructed. For this reason, recent electronic equipment is required to suppress the influence of the noise (hereinafter may be referred to as “noise countermeasure”), as well as to be downsized.
In order to prevent the noise produced in the electronic component from affecting the other electronic component, generally, a filter may be inserted in a noise transmission path to suppress the noise component.
Additionally, the electronic components mounted on the electronic equipment include a D/A converter. The D/A converter is an electronic component widely utilized in an audio function of the electronic equipment or the like, and needs the noise countermeasure especially.
As a conventional noise countermeasure for the D/A converter, for example, the invention of a D/A conversion circuit described in PTL 1 and the like are known. The D/A conversion circuit described in PTL 1 relates to a digital-analog conversion circuit having a high-speed response performance and a low noise performance. The D/A conversion circuit described in PTL 1 includes a reference voltage source circuit, a digital input processing circuit, an weighted current source circuit, and a current controlling switch circuit. Furthermore, at least one of a current buffer circuit and a filter circuit is provided between the weighted current source circuit and the current controlling switch circuit.
FIG. 26 is a circuit diagram illustrating a conventional D/A converter. A sampling circuit 4 includes a sampling capacitor 905 and switches 901, 902, 903, and 904. The switch 901, the sampling capacitor 905 and the switch 902 are connected to one another in series. The switch 903, the sampling capacitor 905 and the switch 904 are connected to one another in series.
The other end of the switch 901 is connected to an input terminal 111 of an analog input signal VREF. The other end of the switch 902 is connected to a terminal 113 to which an analog reference voltage Vcom is supplied. The other end of the switch 904 as an output terminal of the sampling circuit 4 is connected to one end of an integral capacity element 106 and an inverted input terminal of an operational amplifier 107.
The integral capacity element 106 is connected between the inverted input terminal of the operational amplifier 107 and an output terminal. An output terminal of the operational amplifier 107 is connected to the output terminal 112 of the D/A converter 3. An output signal Vout is output from the output terminal 112. A non-inverted input terminal of the operational amplifier 107 is connected to a terminal 114 to which an analog reference voltage Vcom is supplied.
Respective switches mentioned above are driven by clock signals ΦS and ΦI supplied from a controlling circuit 959, and perform on/off operation.
The analog input signal VREF is input from the input terminal 111 to the D/A converter including the above-mentioned configuration. The analog input signal VREF is sampled by the switches 901 and 902. A charge is stored in the sampling capacitor 905 by the sampling.
The charge stored in the sampling capacitor 905 is input to the inverted input terminal of the operational amplifier 107 in accordance with the switching of the switches 901, 902, 903 and 904. The operational amplifier 107 receives the reference voltage signal Vcom at the non-inverted input terminal and outputs the output signal Vout.
FIGS. 27A and 27B are timing charts of clock signals supplied to a conventional D/A converter. FIGS. 27A and 27B illustrate operating timings of the clock signals supplied to the respective switches illustrated in FIG. 26.
The switch 901 and the switch 902 are driven by the clock signal ΦS, and the switch 903 and the switch 904 are driven by the clock signal ΦI.
It is to be noted that FIG. 27A illustrates the clock signal ΦS, and the FIG. 27B illustrates the clock signal ΦI.
As illustrated in FIGS. 27A and 27B, the clock signal ΦS and the clock signal ΦI are non-overlap clock signals, which are not at an H level at the same time.
The sampling timing of the D/A converter illustrated in FIG. 26 comes only when the sampling capacitor 905 performs the sampling operation. Therefore, it is not possible to obtain a Finite Impulse Response (FIR) filter characteristic.
FIG. 28 is a block diagram illustrating filtering in the conventional D/A converter. The conventional filtering uses a D/A converter 1002 and an analog prefilter 1001 to obtain an effect of high-frequency attenuation.